1. Field of the Invention
The present invention relates to a power IC including output power elements with high operating voltage or high blocking capability and their control elements or the like monolithically integrated, and more particularly to such power ICs having an SOI (Silicon On Insulator) structure.
2. Description of the Related Art
An SOI structure can easily obtain high breakdown voltage characteristics and reduce parasitic capacitance, the SOI structure having a laminate of, as shown in FIGS. 1A and 1B, a substrate (hereinafter called a supporting substrate) 1, an SOI insulating film 12, and an Si film (271, 272, 273, 274) stacked in this order from the bottom. If a thin Si film (271, 272, 273, 274) of the SOI structure is used, short channel effects of MOSFETs (MOS Field Effect Transistors) or the like formed in this thin Si film 272, 273 can be suppressed. Therefore, the SOI structure is used as one means for enhancing high integration of elements.
For power ICs having the SOI structure, the Si film (271, 272, . . . ) formed on the SOI insulating film 12 is, as shown in FIGS. 1A. and 1B, generally divided into a plurality of islands 271, 272, 273, . . . by trench element isolation regions 6. More specifically, as shown in FIG. 2, the structure that a power-MOSFET for an output stage (hereinafter called "the output power-MOSFET") is formed in an n-type Si island 172 and a control element such as a CMOS circuit is formed in an n-type island 171, or other structures, are typical and widely used nowadays. In FIG. 2, an n-channel LDMOS (Lateral Double diffused MOS) in the island 172 is used as a high-side switch.
In order to speed up the operation of a power IC, it is necessary to raise a driving voltage of an element so as to apply a high potential difference between the electrodes in or across the elements. The SOI structure such as shown in FIG. 2 has the following deficiencies or problems to be solved in order to realize power switching element with high operating voltage or high blocking voltage.
FIGS. 3A to 3D are schematic cross sectional views of a conventional power IC with an SOI structure. With reference to FIGS. 3A to 3D, some disadvantages of this structure will be explained. FIG. 3A is a schematic cross sectional view illustrating an on-state (conducting state) of an n-channel LDMOS used as a low-side switch, and FIG. 3B is a schematic cross sectional view illustrating an on-state of the n-channel LDMOS used as a high-side switch. In FIG. 3A, an n.sup.+ source region 21 of LDMOS is connected to a ground potential (GND potential), whereas in FIG. 3B, an n.sup.+ drain region 23 of LDMOS is connected to a high potential power source (PS).
As shown in FIG. 3B, with LDMOS used as the high-side switch (the high-side LDMOS), an effective thickness X1' of the drift area formed in an n-type active layer 172 becomes thin and the on-resistance R.sub.ON of the LDMOS increases because an inversion layer 18 is formed. As compared to LDMOS used as the low-side switch (the low-side LDMOS) having an effective thickness X1 of the drift area, generally the same thickness as an n-type active layer 174, the thickness X1' of the high-side LDMOS becomes thinner than X1. The increase of the on-resistance R.sub.ON becomes conspicuous as the active layer 172 becomes thinner, and a substantial reduction in the thickness of the active layer results in a low operation speed of the power IC and other problems such as an increased power dissipation.
In order to change the gate potential of LDMOS so as to follow the source potential thereof, the source of a p-type MOS (pMOS) of CMOS control elements is connected to the source of LDMOS and to the n-type active layer 171 as shown in FIGS. 3C and 3D. The source of an n-type MOS (nMOS) of the CMOS control elements is connected to a power source (PS), for example, +5V. Therefore, as LDMOS changes from an off-state (nonconducting state or current blocking state) to an on-state, the source potential of LDMOS changes from a low potential to a high potential, and as shown in FIG. 3D, the n-type active layer 171 of pMOS changes from a zero potential to a positive high potential. At this time, since the supporting substrate 11 is maintained grounded, a potential difference is generated between the n-type active layer 171 and the supporting substrate 11 and an inversion layer 18 is formed in the n-type active layer 171 on the side of the SOI insulating film 12. A parasitic pnp transistor shown in FIG. 3D is therefore formed, posing a problem that latch-up is more likely to occur during the on-state (FIG. 3D) than the off-state (FIG. 3C).
In a conventional SOI power IC such as shown in FIG. 4A, if an n-type active layer 171 is thin, an inversion layer 18 (p-type conductive layer), induced in the n-type active layer 171 when the off-state of an output stage LDMOS changes to the on-state, electrically connects the two p-type conductive regions 72, 73, or the source region 72 and the drain region 73 constituting a pMOS control element as main electrode regions, and poses a problem of a leakage current.
In order to solve these problems inherent to the SOI structure, it is necessary to prevent the inversion layer 18 from being formed at the bottom of the active layer. To this end, the following two methods have been proposed conventionally.
(1) 1st Method: Changing the potential of the supporting substrate 11 so as to follow the potential of the active layer. For example, in the above example,the source potential of LDMOS is made equal to the potential of the supporting substrate 11.
(2) 2nd Method: The SOI insulating film 12 is made extraordinary thick to reduce the capacitance between the active layer and supporting substrate and correspondingly reduce the charge amount induced at the bottom of the active layer.
The first and second methods for preventing the formation of the inversion layer 18 even if a high potential difference is applied across an element, are, however, associated with the following problems if the methods are applied to a power IC having a plurality of elements formed on an SOI structure and separated by element isolation regions.
(a) If the first method, which changes the potential of the supporting substrate so as to follow the potential of the active layer in order not to generate a potential difference between the active layer in contact with the SOI insulating film and the supporting substrate, is applied to a power IC having a plurality of different type elements formed on the same supporting substrate, the independent operation of each element is lost and some practical problems occur in association with the mutually related operations of other elements on the same supporting substrate.
(b) The second method of using an extraordinary thick SOI insulating film has a practical problem of difficulty in obtaining an effective, sufficient thickness of the SOI insulating film. For example, in order to reduce the charge amount by 1/10, the oxide film is required to be ten times thicker. Heat treatment at a high temperature for a long period of time is required to obtain such a thick oxide film, and this heat treatment may cause crystal defects such as OSFs (Oxidation-induced Stacking Faults). In addition, a large stress is generated at an interface between the thick oxide film and semiconductor, and cracks are likely to be formed in the extraordinary thick oxide film. This method is therefore impractical.